Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.1 (WebPack) - P.15xf Target Family: Spartan3A and Spartan3AN
OS Platform: NT64 Target Device: xc3s700an
Project ID (random number) e821c1ec9712402592e5430b625a4d04.50C16558F1654E55A04E361B0115CA01.34 Target Package: fgg484
Registration ID 175692673_1777502754_0_631 Target Speed: -5
Date Generated 2018-08-15T16:03:42 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=8
  • 3-bit adder=1
  • 4-bit adder=1
  • 6-bit adder=5
  • 7-bit adder=1
 Comparators=35
  • 10-bit comparator greatequal=1
  • 10-bit comparator lessequal=1
  • 13-bit comparator greatequal=2
  • 24-bit comparator equal=1
  • 24-bit comparator greater=3
  • 24-bit comparator less=4
  • 3-bit comparator less=3
  • 4-bit comparator greater=1
  • 6-bit comparator greater=4
  • 6-bit comparator less=1
  • 7-bit comparator greatequal=7
  • 7-bit comparator lessequal=7
 Counters=35
  • 10-bit up counter=1
  • 24-bit up counter=9
  • 3-bit up counter=3
  • 4-bit up counter=2
  • 5-bit up counter=20
 FSMs=6 Latches=2
  • 1-bit latch=1
  • 4-bit latch=1
 Multiplexers=3
  • 32-bit 16-to-1 multiplexer=1
  • 32-bit 4-to-1 multiplexer=1
  • 8-bit 8-to-1 multiplexer=1
 Registers=1568
  • Flip-Flops=1568
 		MiscellaneousStatistics
  • AGG_BONDED_IO=107
  • AGG_IO=107
  • AGG_SLICE=1905
  • NUM_4_INPUT_LUT=1494
  • NUM_BONDED_IBUF=42
  • NUM_BONDED_IOB=65
  • NUM_BUFGMUX=17
  • NUM_CARRY_SKIP=3
  • NUM_CYMUX=487
  • NUM_DCM=4
  • NUM_IOB_FF=33
  • NUM_IOB_LATCH=3
  • NUM_LUT_RT=236
  • NUM_RAMB16BWE=7
  • NUM_RPM=32
  • NUM_SHIFT=5
  • NUM_SLICEL=1838
  • NUM_SLICEM=67
  • NUM_SLICE_FF=2548
  • NUM_SLICE_LATCH=1
  • NUM_XOR=378
  • Xilinx Core C_COUNTER_BINARY_V6_0, Coregen 9.2.04i_ip2=5
  • Xilinx Core C_REG_FD_V7_0, Coregen 9.2.04i_ip2=8
  • Xilinx Core C_SHIFT_FD_V6_0, Coregen 9.2.04i_ip2=2
  • Xilinx Core C_SHIFT_FD_V7_0, Coregen 9.2.04i_ip2=4
  • Xilinx Core blk_mem_gen_v2_6, Coregen 9.2.04i_ip2=3
  • Xilinx Core c_counter_binary_v8_0, Coregen 9.2.04i_ip2=20
  • Xilinx Core dist_mem_gen_v3_3, Coregen 9.2.04i_ip2=1
  • Xilinx Core fifo_generator_v4_2, Coregen 9.2.04i_ip2=2
  • Xilinx Core mult_gen_v10_0, Coregen 9.2.04i_ip2=2
 		NetStatistics
  • NumNets_Active=3732
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=112
  • NumNodesOfType_Active_BRAMDUMMY=350
  • NumNodesOfType_Active_CLKPIN=1717
  • NumNodesOfType_Active_CNTRLPIN=1815
  • NumNodesOfType_Active_DOUBLE=6022
  • NumNodesOfType_Active_DUMMY=3856
  • NumNodesOfType_Active_DUMMYBANK=162
  • NumNodesOfType_Active_DUMMYESC=24
  • NumNodesOfType_Active_GLOBAL=330
  • NumNodesOfType_Active_HFULLHEX=66
  • NumNodesOfType_Active_HLONG=23
  • NumNodesOfType_Active_HUNIHEX=390
  • NumNodesOfType_Active_INPUT=6680
  • NumNodesOfType_Active_IOBOUTPUT=55
  • NumNodesOfType_Active_OMUX=3824
  • NumNodesOfType_Active_OUTPUT=3582
  • NumNodesOfType_Active_PREBXBY=2946
  • NumNodesOfType_Active_VFULLHEX=504
  • NumNodesOfType_Active_VLONG=113
  • NumNodesOfType_Active_VUNIHEX=621
  • NumNodesOfType_Gnd_BRAMADDR=22
  • NumNodesOfType_Gnd_BRAMDUMMY=58
  • NumNodesOfType_Gnd_CLKPIN=4
  • NumNodesOfType_Gnd_CNTRLPIN=10
  • NumNodesOfType_Gnd_DOUBLE=69
  • NumNodesOfType_Gnd_DUMMY=20
  • NumNodesOfType_Gnd_DUMMYBANK=15
  • NumNodesOfType_Gnd_INPUT=142
  • NumNodesOfType_Gnd_OMUX=59
  • NumNodesOfType_Gnd_OUTPUT=50
  • NumNodesOfType_Gnd_PREBXBY=47
  • NumNodesOfType_Gnd_VFULLHEX=4
  • NumNodesOfType_Vcc_BRAMDUMMY=8
  • NumNodesOfType_Vcc_CNTRLPIN=15
  • NumNodesOfType_Vcc_INPUT=37
  • NumNodesOfType_Vcc_PREBXBY=26
  • NumNodesOfType_Vcc_VCCOUT=39
 SiteStatistics
  • IBUF-DIFFMI_NDT=14
  • IBUF-DIFFMLR=1
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSI_NDT=13
  • IBUF-DIFFSTB=3
  • IOB-DIFFMLR=21
  • IOB-DIFFMTB=13
  • IOB-DIFFSLR=15
  • IOB-DIFFSTB=16
  • SLICEL-SLICEM=825
 		SiteSummary
  • BUFGMUX=17
  • BUFGMUX_GCLKMUX=17
  • BUFGMUX_GCLK_BUFFER=17
  • DCM=4
  • DCM_DCM=4
  • IBUF=42
  • IBUF_DELAY_ADJ_BBOX=42
  • IBUF_IFF1=23
  • IBUF_INBUF=42
  • IBUF_PAD=42
  • IOB=65
  • IOB_DELAY_ADJ_BBOX=8
  • IOB_IFF1=8
  • IOB_INBUF=8
  • IOB_OFF1=5
  • IOB_OUTBUF=65
  • IOB_PAD=65
  • RAMB16BWE=7
  • RAMB16BWE_RAMB16BWE=7
  • SLICEL=1838
  • SLICEL_C1VDD=32
  • SLICEL_C2VDD=15
  • SLICEL_CYMUXF=261
  • SLICEL_CYMUXG=226
  • SLICEL_F=627
  • SLICEL_F5MUX=125
  • SLICEL_F6MUX=40
  • SLICEL_FFX=978
  • SLICEL_FFY=1566
  • SLICEL_G=734
  • SLICEL_GNDF=198
  • SLICEL_GNDG=180
  • SLICEL_VDDG=3
  • SLICEL_XORF=193
  • SLICEL_XORG=185
  • SLICEM=67
  • SLICEM_F=66
  • SLICEM_F5MUX=64
  • SLICEM_F6MUX=64
  • SLICEM_FFX=2
  • SLICEM_FFY=3
  • SLICEM_G=67
  • SLICEM_WSGEN=3
 
Configuration Data
BUFGMUX
  • S=[S_INV:15] [S:2]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[HIGH:2] [LOW:15]
  • S=[S_INV:15] [S:2]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:4]
  • PSEN=[PSEN_INV:0] [PSEN:4]
  • PSINCDEC=[PSINCDEC:4] [PSINCDEC_INV:0]
  • RST=[RST:4] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2:4]
  • CLKOUT_PHASE_SHIFT=[FIXED:4]
  • CLK_FEEDBACK=[1X:4]
  • DESKEW_ADJUST=[8:4]
  • DFS_FREQUENCY_MODE=[LOW:4]
  • DLL_FREQUENCY_MODE=[LOW:4]
  • DUTY_CYCLE_CORRECTION=[TRUE:4]
  • FACTORY_JF1=[0XC0:4]
  • FACTORY_JF2=[0X80:4]
  • PSCLK=[PSCLK_INV:0] [PSCLK:4]
  • PSEN=[PSEN_INV:0] [PSEN:4]
  • PSINCDEC=[PSINCDEC:4] [PSINCDEC_INV:0]
  • RST=[RST:4] [RST_INV:0]
 IBUF
  • ICLK1=[ICLK1_INV:0] [ICLK1:23]
  • SR=[SR:0] [SR_INV:2]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:42]
  • IBUF_DELAY_VALUE=[DLY0:42]
  • IFD_DELAY_VALUE=[DLY0:19] [DLY5:23]
  • SEL_IN=[SEL_IN:42] [SEL_IN_INV:0]
 IBUF_IFF1
  • CK=[CK:23] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:23]
  • IFF1_SR_ATTR=[SRLOW:2]
  • IFFATTRBOX=[ASYNC:2]
  • LATCH_OR_FF=[FF:23]
  • SR=[SR:0] [SR_INV:2]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:42]
  • PULL=[PULLUP:4] [PULLDOWN:9]
 IOB
  • ICLK1=[ICLK1_INV:0] [ICLK1:8]
  • O1=[O1_INV:1] [O1:64]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:5]
  • SR=[SR:0] [SR_INV:8]
  • T1=[T1_INV:0] [T1:10]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:8]
  • IBUF_DELAY_VALUE=[DLY0:8]
  • IFD_DELAY_VALUE=[DLY5:8]
  • SEL_IN=[SEL_IN:8] [SEL_IN_INV:0]
 IOB_IFF1
  • CK=[CK:8] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:8]
  • IFF1_SR_ATTR=[SRLOW:8]
  • IFFATTRBOX=[ASYNC:8]
  • LATCH_OR_FF=[FF:8]
  • SR=[SR:0] [SR_INV:8]
 IOB_OFF1
  • CK=[CK:5] [CK_INV:0]
  • D=[D:5] [D_INV:0]
  • LATCH_OR_FF=[FF:2] [LATCH:3]
  • OFF1_INIT_ATTR=[INIT0:5]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:64]
  • SUSPEND=[3STATE:65]
  • TRI=[TRI_INV:0] [TRI:10]
 IOB_PAD
  • DRIVEATTRBOX=[8:16] [12:49]
  • IOATTRBOX=[LVCMOS33:65]
  • PULL=[PULLUP:1]
  • SLEW=[SLOW:65]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:7]
  • CLKB=[CLKB_INV:0] [CLKB:7]
  • ENA=[ENA_INV:0] [ENA:7]
  • ENB=[ENB_INV:0] [ENB:7]
  • SSRA=[SSRA_INV:0] [SSRA:7]
  • SSRB=[SSRB_INV:0] [SSRB:7]
  • WEA0=[WEA0:7] [WEA0_INV:0]
  • WEA1=[WEA1:7] [WEA1_INV:0]
  • WEA2=[WEA2:7] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:7]
  • WEB0=[WEB0:7] [WEB0_INV:0]
  • WEB1=[WEB1:7] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:7]
  • WEB3=[WEB3:7] [WEB3_INV:0]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:7]
  • CLKB=[CLKB_INV:0] [CLKB:7]
  • DATA_WIDTH_A=[18:4] [36:3]
  • DATA_WIDTH_B=[18:4] [36:3]
  • ENA=[ENA_INV:0] [ENA:7]
  • ENB=[ENB_INV:0] [ENB:7]
  • SSRA=[SSRA_INV:0] [SSRA:7]
  • SSRB=[SSRB_INV:0] [SSRB:7]
  • WEA0=[WEA0:7] [WEA0_INV:0]
  • WEA1=[WEA1:7] [WEA1_INV:0]
  • WEA2=[WEA2:7] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:7]
  • WEB0=[WEB0:7] [WEB0_INV:0]
  • WEB1=[WEB1:7] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:7]
  • WEB3=[WEB3:7] [WEB3_INV:0]
  • WRITE_MODE_A=[NO_CHANGE:3] [WRITE_FIRST:4]
  • WRITE_MODE_B=[NO_CHANGE:3] [WRITE_FIRST:4]
 SLICEL
  • BX=[BX_INV:7] [BX:775]
  • BY=[BY:1194] [BY_INV:26]
  • CE=[CE:682] [CE_INV:46]
  • CIN=[CIN_INV:0] [CIN:219]
  • CLK=[CLK:1654] [CLK_INV:2]
  • SR=[SR:977] [SR_INV:80]
 SLICEL_CYMUXF
  • 0=[0:261] [0_INV:0]
  • 1=[1_INV:4] [1:257]
 SLICEL_CYMUXG
  • 0=[0:223] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:125] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:40] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:351] [CE_INV:17]
  • CK=[CK:978] [CK_INV:0]
  • D=[D:975] [D_INV:3]
  • FFX_INIT_ATTR=[INIT0:924] [INIT1:54]
  • FFX_SR_ATTR=[SRLOW:923] [SRHIGH:55]
  • LATCH_OR_FF=[FF:978]
  • REV=[REV_INV:0] [REV:9]
  • SR=[SR:643] [SR_INV:64]
  • SYNC_ATTR=[ASYNC:607] [SYNC:371]
 SLICEL_FFY
  • CE=[CE:676] [CE_INV:40]
  • CK=[CK:1564] [CK_INV:2]
  • D=[D:1540] [D_INV:26]
  • FFY_INIT_ATTR=[INIT0:1473] [INIT1:93]
  • FFY_SR_ATTR=[SRLOW:1461] [SRHIGH:105]
  • LATCH_OR_FF=[FF:1565] [LATCH:1]
  • SR=[SR:896] [SR_INV:79]
  • SYNC_ATTR=[ASYNC:1031] [SYNC:535]
 SLICEL_XORF
  • 1=[1_INV:4] [1:189]
 SLICEM
  • BX=[BX_INV:0] [BX:66]
  • BY=[BY:67] [BY_INV:0]
  • CE=[CE:0] [CE_INV:3]
  • CLK=[CLK:3] [CLK_INV:0]
  • SR=[SR:0] [SR_INV:3]
 SLICEM_F
  • DI=[DI:2] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:2]
  • LUT_OR_MEM=[LUT:64] [RAM:2]
 SLICEM_F5MUX
  • S0=[S0:64] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:64] [S0_INV:0]
 SLICEM_FFX
  • CE=[CE:0] [CE_INV:2]
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:2]
  • FFX_SR_ATTR=[SRLOW:2]
  • LATCH_OR_FF=[FF:2]
  • SYNC_ATTR=[ASYNC:2]
 SLICEM_FFY
  • CE=[CE:0] [CE_INV:3]
  • CK=[CK:3] [CK_INV:0]
  • D=[D:3] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:3]
  • FFY_SR_ATTR=[SRLOW:3]
  • LATCH_OR_FF=[FF:3]
  • SYNC_ATTR=[ASYNC:3]
 SLICEM_G
  • DI=[DI:3] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:3]
  • LUT_OR_MEM=[LUT:64] [RAM:3]
 SLICEM_WSGEN
  • CK=[CK:3] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:3]
  • WE=[WE_INV:3] [WE:0]
 
Pin Data
BUFGMUX
  • I0=17
  • I1=2
  • O=17
  • S=17
 BUFGMUX_GCLKMUX
  • I0=17
  • I1=2
  • OUT=17
  • S=17
 BUFGMUX_GCLK_BUFFER
  • IN=17
  • OUT=17
 DCM
  • CLK0=4
  • CLK180=1
  • CLK270=1
  • CLKDV=1
  • CLKFB=4
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=4
  • LOCKED=3
  • PSCLK=4
  • PSEN=4
  • PSINCDEC=4
  • RST=4
  • STATUS2=1
 DCM_DCM
  • CLK0=4
  • CLK180=1
  • CLK270=1
  • CLKDV=1
  • CLKFB=4
  • CLKFX=1
  • CLKFX180=1
  • CLKIN=4
  • LOCKED=3
  • PSCLK=4
  • PSEN=4
  • PSINCDEC=4
  • RST=4
  • STATUS2=1
 IBUF
  • I=24
  • ICLK1=23
  • IQ1=23
  • PAD=42
  • SR=2
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=24
  • IFD_OUT=23
  • SEL_IN=42
 IBUF_IFF1
  • CK=23
  • D=23
  • Q=23
  • SR=2
 IBUF_INBUF
  • IN=42
  • OUT=42
 IBUF_PAD
  • PAD=42
 IOB
  • ICLK1=8
  • IQ1=8
  • O1=65
  • OTCLK1=5
  • PAD=65
  • SR=8
  • T1=10
 IOB_DELAY_ADJ_BBOX
  • IFD_OUT=8
  • SEL_IN=8
 IOB_IFF1
  • CK=8
  • D=8
  • Q=8
  • SR=8
 IOB_INBUF
  • IN=8
  • OUT=8
 IOB_OFF1
  • CK=5
  • D=5
  • Q=5
 IOB_OUTBUF
  • IN=65
  • OUT=65
  • TRI=10
 IOB_PAD
  • PAD=65
 RAMB16BWE
  • ADDRA10=7
  • ADDRA11=7
  • ADDRA12=7
  • ADDRA13=7
  • ADDRA4=4
  • ADDRA5=7
  • ADDRA6=7
  • ADDRA7=7
  • ADDRA8=7
  • ADDRA9=7
  • ADDRB10=7
  • ADDRB11=7
  • ADDRB12=7
  • ADDRB13=7
  • ADDRB4=4
  • ADDRB5=7
  • ADDRB6=7
  • ADDRB7=7
  • ADDRB8=7
  • ADDRB9=7
  • CLKA=7
  • CLKB=7
  • DIA0=7
  • DIA1=7
  • DIA10=7
  • DIA11=7
  • DIA12=7
  • DIA13=7
  • DIA14=7
  • DIA15=7
  • DIA16=3
  • DIA17=3
  • DIA18=3
  • DIA19=3
  • DIA2=7
  • DIA20=3
  • DIA21=3
  • DIA22=3
  • DIA23=3
  • DIA24=3
  • DIA25=3
  • DIA26=3
  • DIA27=3
  • DIA28=3
  • DIA29=3
  • DIA3=7
  • DIA30=3
  • DIA31=3
  • DIA4=7
  • DIA5=7
  • DIA6=7
  • DIA7=7
  • DIA8=7
  • DIA9=7
  • DIPA0=7
  • DIPA1=7
  • DIPA2=3
  • DIPA3=3
  • DOB0=6
  • DOB1=6
  • DOB10=7
  • DOB11=7
  • DOB12=7
  • DOB13=7
  • DOB14=7
  • DOB15=5
  • DOB16=3
  • DOB17=3
  • DOB18=3
  • DOB19=3
  • DOB2=6
  • DOB20=3
  • DOB21=3
  • DOB22=3
  • DOB23=3
  • DOB24=3
  • DOB25=3
  • DOB26=3
  • DOB27=3
  • DOB28=3
  • DOB29=3
  • DOB3=6
  • DOB30=3
  • DOB31=3
  • DOB4=6
  • DOB5=6
  • DOB6=6
  • DOB7=4
  • DOB8=7
  • DOB9=7
  • DOPB0=2
  • DOPB1=2
  • ENA=7
  • ENB=7
  • SSRA=7
  • SSRB=7
  • WEA0=7
  • WEA1=7
  • WEA2=7
  • WEA3=7
  • WEB0=7
  • WEB1=7
  • WEB2=7
  • WEB3=7
 RAMB16BWE_RAMB16BWE
  • ADDRA10=7
  • ADDRA11=7
  • ADDRA12=7
  • ADDRA13=7
  • ADDRA4=4
  • ADDRA5=7
  • ADDRA6=7
  • ADDRA7=7
  • ADDRA8=7
  • ADDRA9=7
  • ADDRB10=7
  • ADDRB11=7
  • ADDRB12=7
  • ADDRB13=7
  • ADDRB4=4
  • ADDRB5=7
  • ADDRB6=7
  • ADDRB7=7
  • ADDRB8=7
  • ADDRB9=7
  • CLKA=7
  • CLKB=7
  • DIA0=7
  • DIA1=7
  • DIA10=7
  • DIA11=7
  • DIA12=7
  • DIA13=7
  • DIA14=7
  • DIA15=7
  • DIA16=3
  • DIA17=3
  • DIA18=3
  • DIA19=3
  • DIA2=7
  • DIA20=3
  • DIA21=3
  • DIA22=3
  • DIA23=3
  • DIA24=3
  • DIA25=3
  • DIA26=3
  • DIA27=3
  • DIA28=3
  • DIA29=3
  • DIA3=7
  • DIA30=3
  • DIA31=3
  • DIA4=7
  • DIA5=7
  • DIA6=7
  • DIA7=7
  • DIA8=7
  • DIA9=7
  • DIPA0=7
  • DIPA1=7
  • DIPA2=3
  • DIPA3=3
  • DOB0=6
  • DOB1=6
  • DOB10=7
  • DOB11=7
  • DOB12=7
  • DOB13=7
  • DOB14=7
  • DOB15=5
  • DOB16=3
  • DOB17=3
  • DOB18=3
  • DOB19=3
  • DOB2=6
  • DOB20=3
  • DOB21=3
  • DOB22=3
  • DOB23=3
  • DOB24=3
  • DOB25=3
  • DOB26=3
  • DOB27=3
  • DOB28=3
  • DOB29=3
  • DOB3=6
  • DOB30=3
  • DOB31=3
  • DOB4=6
  • DOB5=6
  • DOB6=6
  • DOB7=4
  • DOB8=7
  • DOB9=7
  • DOPB0=2
  • DOPB1=2
  • ENA=7
  • ENB=7
  • SSRA=7
  • SSRB=7
  • WEA0=7
  • WEA1=7
  • WEA2=7
  • WEA3=7
  • WEB0=7
  • WEB1=7
  • WEB2=7
  • WEB3=7
 SLICEL
  • BX=782
  • BY=1220
  • CE=728
  • CIN=219
  • CLK=1656
  • COUT=226
  • F1=621
  • F2=465
  • F3=342
  • F4=137
  • F5=80
  • FX=32
  • FXINA=40
  • FXINB=40
  • G1=730
  • G2=582
  • G3=401
  • G4=133
  • SR=1057
  • X=154
  • XB=11
  • XQ=978
  • Y=208
  • YQ=1566
 SLICEL_C1VDD
  • 1=32
 SLICEL_C2VDD
  • 1=15
 SLICEL_CYMUXF
  • 0=261
  • 1=261
  • OUT=261
  • S0=261
 SLICEL_CYMUXG
  • 0=223
  • 1=226
  • OUT=226
  • S0=226
 SLICEL_F
  • A1=621
  • A2=465
  • A3=342
  • A4=137
  • D=627
 SLICEL_F5MUX
  • F=125
  • G=125
  • OUT=125
  • S0=125
 SLICEL_F6MUX
  • 0=40
  • 1=40
  • OUT=40
  • S0=40
 SLICEL_FFX
  • CE=368
  • CK=978
  • D=978
  • Q=978
  • REV=9
  • SR=707
 SLICEL_FFY
  • CE=716
  • CK=1566
  • D=1566
  • Q=1566
  • SR=975
 SLICEL_G
  • A1=730
  • A2=582
  • A3=401
  • A4=133
  • D=734
 SLICEL_GNDF
  • 0=198
 SLICEL_GNDG
  • 0=180
 SLICEL_VDDG
  • 1=3
 SLICEL_XORF
  • 0=193
  • 1=193
  • O=193
 SLICEL_XORG
  • 0=185
  • 1=185
  • O=185
 SLICEM
  • BX=66
  • BY=67
  • CE=3
  • CLK=3
  • F1=66
  • F2=66
  • F3=66
  • F4=2
  • F5=64
  • FX=32
  • FXINA=64
  • FXINB=64
  • G1=67
  • G2=67
  • G3=67
  • G4=3
  • SR=3
  • XQ=2
  • Y=32
  • YQ=3
 SLICEM_F
  • A1=66
  • A2=66
  • A3=66
  • A4=2
  • D=66
  • DI=2
  • WS=2
 SLICEM_F5MUX
  • F=64
  • G=64
  • OUT=64
  • S0=64
 SLICEM_F6MUX
  • 0=64
  • 1=64
  • OUT=64
  • S0=64
 SLICEM_FFX
  • CE=2
  • CK=2
  • D=2
  • Q=2
 SLICEM_FFY
  • CE=3
  • CK=3
  • D=3
  • Q=3
 SLICEM_G
  • A1=67
  • A2=67
  • A3=67
  • A4=3
  • D=67
  • DI=3
  • WS=3
 SLICEM_WSGEN
  • CK=3
  • WE=3
  • WSF=2
  • WSG=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s700an-fgg484-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s700an-fgg484-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 12 12 0 0 0 0 0
bitgen 27 27 0 0 0 0 0
cse_server 14 14 0 0 0 0 0
edif2ngd 868 867 0 0 0 0 0
map 32 28 0 0 0 0 0
netgen 28 28 0 0 0 0 0
ngc2edif 22 22 0 0 0 0 0
ngcbuild 32 32 0 0 0 0 0
ngdbuild 33 32 0 0 0 0 0
par 28 28 0 0 0 0 0
trce 28 28 0 0 0 0 0
xst 50 47 0 0 0 0 0
 
Help Statistics
Search words with results
COE ( 1 ) COE file ( 1 )
KEEP ( 1 ) KEEP VALUE ( 1 )
SAIF ( 1 ) saif ( 1 )
signal rate ( 1 ) vcd ( 1 )
Unsuccessful Search words
vcd2saif ( 1 )
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_define_mem_contents.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_define_values_coe_file.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_overview.htm ( 1 )
/doc/usenglish/isehelp/cgn_r_coe_file_syntax.htm ( 1 ) /doc/usenglish/isehelp/cgn_r_core_generator_input_files.htm ( 1 )
/doc/usenglish/isehelp/ise_c_debugging_strategies_chipscope_pro.htm ( 1 ) /doc/usenglish/isehelp/ise_c_debugging_strategies_using_fpga_editor.htm ( 1 )
/doc/usenglish/isehelp/ise_c_implement_fpga_design.htm ( 1 ) /doc/usenglish/isehelp/ise_c_overview.htm ( 1 )
/doc/usenglish/isehelp/ise_c_process_analyze_design_using_chipscope.htm ( 1 ) /doc/usenglish/isehelp/ise_c_sim_environment.htm ( 1 )
/doc/usenglish/isehelp/ise_c_simulation_timing.htm ( 1 ) /doc/usenglish/isehelp/ise_c_xst_performance_strategies.htm ( 1 )
/doc/usenglish/isehelp/ise_p_running_chipscope_pro_inserter.htm ( 1 ) /doc/usenglish/isehelp/pim_db_file_generation_preferences.htm ( 1 )
/doc/usenglish/isehelp/pn_db_design_properties.htm ( 1 ) /doc/usenglish/isehelp/pn_db_editor_options.htm ( 1 )
/doc/usenglish/isehelp/pp_db_configuration_options.htm ( 1 ) /doc/usenglish/isehelp/pp_db_configure_target_device_properties.htm ( 1 )
/doc/usenglish/isehelp/pp_db_fitting_properties.htm ( 1 ) /doc/usenglish/isehelp/pp_db_map_properties.htm ( 1 )
/doc/usenglish/isehelp/pp_db_place_and_route_properties.htm ( 1 ) /doc/usenglish/isehelp/pp_db_simulation_properties.htm ( 1 )
/doc/usenglish/isehelp/pp_db_startup_options.htm ( 1 ) /doc/usenglish/isehelp/pp_db_xst_synthesis_options.htm ( 1 )
/doc/usenglish/isehelp/spartan3a/libs_le_dcm_sp.htm ( 1 ) /doc/usenglish/isehelp/spartan3a/libs_le_fd.htm ( 1 )
/doc/usenglish/isehelp/spartan3a/libs_le_fdcp.htm ( 1 ) /doc/usenglish/isehelp/spartan3a/libs_le_fdr.htm ( 1 )
/doc/usenglish/isehelp/spartan3a/libs_le_fdrs.htm ( 1 ) /doc/usenglish/isehelp/spartan3a/libs_le_iobuf.htm ( 1 )
/doc/usenglish/isehelp/sse_db_new_attribute.htm ( 1 ) /doc/usenglish/isehelp/sse_db_sch_prop_bus_rename.htm ( 1 )
/doc/usenglish/isehelp/sse_p_adding_attr.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_xilinx_constraints.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_accuracy_checklist.htm ( 1 ) /doc/usenglish/isehelp/xpa_c_frequency.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_overview.htm ( 1 ) /doc/usenglish/isehelp/xpa_c_signal_rate.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_togglerates.htm ( 1 ) /doc/usenglish/isehelp/xpa_c_typesview.htm ( 1 )
/doc/usenglish/isehelp/xpa_p_setting_toggle_rates.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Timing Performance
PROP_LastAppliedStrategy=Performance with IOB Packing;C:/Xilinx/14.1/ISE_DS/ISE/spartan3a/data/spartan3a_performance_with_iobpacking.xds PROP_ManualCompileOrderImp=false
PROP_OverwriteSym=true PROP_PropSpecInProjFile=Store all values
PROP_Simulator=Modelsim-PE VHDL PROP_SynthOptEffort=High
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=Schematic
PROP_UseSmartGuide=false PROP_UserBrowsedStrategyFiles=C:/Xilinx/14.1/ISE_DS/ISE/spartan3a/data/spartan3a_performance_with_iobpacking.xds
PROP_UserConstraintEditorPreference=Text Editor PROP_UserEditorCustomSetting=scriptum.exe $1
PROP_UserEditorPreference=Custom PROP_intProjectCreationTimestamp=2016-09-05T12:39:41
PROP_intWbtProjectID=50C16558F1654E55A04E361B0115CA01 PROP_intWbtProjectIteration=34
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xilxMapPackRegInto=For Inputs and Outputs
PROP_xilxMapTimingDrivenPacking=true PROP_xilxPARplacerEffortLevel=High
PROP_xilxPARrouterEffortLevel=High PROP_xilxSynthKeepHierarchy=Soft
PROP_xilxSynthRegBalancing=Yes PROP_xstPackIORegister=Yes
PROP_AutoTop=true PROP_DevFamily=Spartan3A and Spartan3AN
PROP_parGenSimModel=true PROP_DevDevice=xc3s700an
PROP_DevFamilyPMName=spartan3a PROP_MapExtraEffort=Normal
PROP_xilxPARextraEffortLevel=Normal PROP_DevPackage=fgg484
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_COREGEN=28
FILE_NGC=4 FILE_NGO=1
FILE_SCHEMATIC=14 FILE_UCF=1
FILE_VHDL=22
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=1 NGDBUILD_NUM_AND2B1=29 NGDBUILD_NUM_AND4B2=1 NGDBUILD_NUM_BUF=57
NGDBUILD_NUM_BUFG=17 NGDBUILD_NUM_BUFGMUX_1=2 NGDBUILD_NUM_DCM_SP=4 NGDBUILD_NUM_FD=58
NGDBUILD_NUM_FDC=453 NGDBUILD_NUM_FDCE=237 NGDBUILD_NUM_FDCP=10 NGDBUILD_NUM_FDCPE=3
NGDBUILD_NUM_FDE=702 NGDBUILD_NUM_FDP=25 NGDBUILD_NUM_FDPE=18 NGDBUILD_NUM_FDR=642
NGDBUILD_NUM_FDRE=136 NGDBUILD_NUM_FDS=100 NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=46
NGDBUILD_NUM_IBUF=38 NGDBUILD_NUM_IBUFG=4 NGDBUILD_NUM_INV=72 NGDBUILD_NUM_IOBUF=8
NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LD_1=3 NGDBUILD_NUM_LUT1=256 NGDBUILD_NUM_LUT2=210
NGDBUILD_NUM_LUT2_L=5 NGDBUILD_NUM_LUT3=607 NGDBUILD_NUM_LUT3_L=3 NGDBUILD_NUM_LUT4=298
NGDBUILD_NUM_LUT4_L=5 NGDBUILD_NUM_MUXCY=530 NGDBUILD_NUM_MUXF5=189 NGDBUILD_NUM_MUXF6=72
NGDBUILD_NUM_MUXF7=32 NGDBUILD_NUM_NAND2B1=24 NGDBUILD_NUM_NAND2B2=3 NGDBUILD_NUM_NAND3B3=3
NGDBUILD_NUM_OBUF=55 NGDBUILD_NUM_OBUFT=2 NGDBUILD_NUM_OR2=19 NGDBUILD_NUM_OR2B1=1
NGDBUILD_NUM_OR2B2=1 NGDBUILD_NUM_OR3=1 NGDBUILD_NUM_OR3B1=1 NGDBUILD_NUM_RAMB16BWE=7
NGDBUILD_NUM_SRLC16E=5 NGDBUILD_NUM_VCC=48 NGDBUILD_NUM_XORCY=397
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=1 NGDBUILD_NUM_AND2B1=29 NGDBUILD_NUM_AND4B2=1 NGDBUILD_NUM_BUF=64
NGDBUILD_NUM_BUFG=17 NGDBUILD_NUM_BUFGMUX_1=2 NGDBUILD_NUM_DCM_SP=4 NGDBUILD_NUM_FD=58
NGDBUILD_NUM_FDC=453 NGDBUILD_NUM_FDCE=429 NGDBUILD_NUM_FDCP=10 NGDBUILD_NUM_FDCPE=3
NGDBUILD_NUM_FDE=921 NGDBUILD_NUM_FDP=25 NGDBUILD_NUM_FDPE=22 NGDBUILD_NUM_FDR=642
NGDBUILD_NUM_FDRE=177 NGDBUILD_NUM_FDS=100 NGDBUILD_NUM_FDSE=17 NGDBUILD_NUM_GND=110
NGDBUILD_NUM_IBUF=46 NGDBUILD_NUM_IBUFG=4 NGDBUILD_NUM_INV=72 NGDBUILD_NUM_LDC=1
NGDBUILD_NUM_LD_1=3 NGDBUILD_NUM_LUT1=256 NGDBUILD_NUM_LUT2=210 NGDBUILD_NUM_LUT2_L=5
NGDBUILD_NUM_LUT3=607 NGDBUILD_NUM_LUT3_L=3 NGDBUILD_NUM_LUT4=495 NGDBUILD_NUM_LUT4_L=5
NGDBUILD_NUM_MUXCY=551 NGDBUILD_NUM_MUXF5=189 NGDBUILD_NUM_MUXF6=72 NGDBUILD_NUM_MUXF7=32
NGDBUILD_NUM_NAND2B1=24 NGDBUILD_NUM_NAND2B2=3 NGDBUILD_NUM_NAND3B3=3 NGDBUILD_NUM_OBUF=55
NGDBUILD_NUM_OBUFT=10 NGDBUILD_NUM_OR2=19 NGDBUILD_NUM_OR2B1=1 NGDBUILD_NUM_OR2B2=1
NGDBUILD_NUM_OR3=1 NGDBUILD_NUM_OR3B1=1 NGDBUILD_NUM_PULLDOWN=9 NGDBUILD_NUM_PULLUP=5
NGDBUILD_NUM_RAMB16BWE=7 NGDBUILD_NUM_SRLC16E=5 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=112
NGDBUILD_NUM_XORCY=423
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s700an-5-fgg484 -top=<design_top> -opt_mode=Speed -opt_level=2
-iuc=NO -keep_hierarchy=Soft -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=Yes -move_first_stage=YES -move_last_stage=YES
-optimize_primitives=NO -use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes
-iob=True -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5